1. Field of the Invention
This invention relates generally to semiconductor memory devices and more particularly to a column select line enable circuit for a semiconductor memory device.
2. Description of the Related Art
In a synchronous dynamic random access memory (SDRAM), row active commands and read/write commands are input in synchronization with a system clock, as are various other commands for executing functions of the SDRAM. Input/output operations occur at either the rising edge or the falling edge of the system clock depending on the design of the particular SDRAM.
Although signals applied to an SDRAM from outside the chip are synchronized with the system clock, the internal circuitry within the SDRAM is divided into a clock-synchronous portion and a clock-asynchronous portion. The clock-synchronous portion is further sub-divided into a portion operating in synchronization with an externally applied system clock signal and a portion operating in synchronization with an internally generated clock signal. For example, whereas row address decoding, selected word line activation, or bit line sensing operations are executed asynchronously, data input/output operations of the semiconductor memory device are executed in synchronization with the clock.
A predetermined time margin is required for interfacing between the synchronous and asynchronous portions of an SDRAM. If the time margin for interface is not secured, malfunctions which reduce reliability may occur. In order to attain high-speed operation while maintaining excellent operational reliability, the required time margin known as tRCD must be reduced. The tRCD parameter (/RAS to /CAS delay) is the minimum time required form the time a row active command is input to the time a read/write command is input.
FIG. 4 is a timing diagram for explaining the parameter tRCD in an SDRAM device. In FIG. 4, tCC denotes the cycle time of the system clock. A chip select signal /CS, which is a "low" level active signal, is input to a semiconductor memory device at the rising edge of the system clock CLK. A row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE, all of which are active "low", are input at the rising edge of the system clock CLK.
A row active command and a read command are carried out through a combination of the write enable signal /WE, the chip select signal /CS, the column address strobe signal /CAS and the row address strobe signal /RAS.
When the semiconductor memory device is in an idle state, the combination of a "low" level chip select signal /CS, a "low" level row address strobe signal /RAS, a "high" level column address strobe signal /CAS and a "high" level write enable signal /WE is recognized as a row active command at the rising edge of the system clock CLK.
When the semiconductor memory device is in a row active state, a "low" level chip select signal /CS, "high" level row address strobe signal /RAS, "low" level column address strobe signal /CAS and "high" level write enable signal /WE are recognized as a read command at the rising edge of the system clock CLK.
Other combinations can also be used to implement other commands.
FIG. 5 is a waveform diagram showing the operation of internal signals in the semiconductor memory device when the row active command and the read command are input to the device.
When the row active command is input, a word line corresponding to a row selected according to a bank address and a row address becomes active. Then, a bit line sensing operation is executed so that a level transition on the bit line occurs. Here, t1 is the time required from the input time of the row active command to the occurrence of the bit line sensing operation, and t2 is the time from the input time of read/write command to the enabling time of a column select line. If the column select line signal CSLi becomes active prior to t1, a malfunction may occur. Thus, tRCD is determined on the basis of t1.
For example, assume the cycle time tCC of the clock is 10 ns (that is, the frequency of the clock is 100 MHz), t1 of a first semiconductor memory device "A" is 30 ns, and t2 of device A is 10 ns. Also assume that t1 of a second semiconductor memory device "B" is 31 ns, and t2 of device B is 10 ns. In this case, tRCD of device A is 2 clocks, and that of the semiconductor memory device B is 3 clocks. Then, the difference between t1 values of the semiconductor memory devices, i.e., Ins, is equivalent to 1 clock difference between tRCD values of the semiconductor memory devices. This is because all commands are input in synchronization with the system clock CLK. In other words, the semiconductor memory device B will experience a malfunction when a read command is applied only 2 cycles after a row active command is applied.
FIG. 1 is schematic diagram of a conventional column select line enable circuit of a semiconductor memory device. The circuit of FIG. 1 includes inverters 110, 120 and 150, a NOR gate 130, and a NAND gate 140. There is one conventional column select line enable circuit for each bank. For example, when the number of banks included in the semiconductor memory device is two, two column select line enable circuits are included.
Referring to FIG. 1, the inverter 110 inverts a decoded bank address signal DBAi. A one bit bank address is applied from outside the semiconductor memory device if there are two banks. Bank A is selected when the bank address composed of one bit is in a logic "low" level, and a bank B is selected if the bank address is in a logic "high" level. If 1-bit bank address is decoded, two decoded bank address signal are output. Of the two output signals, one corresponds to bank A, while the other corresponds to bank B. Therefore, the decoded bank address signal is activated, i.e., driven to a "high" level, only if the corresponding bank is selected.
A timing control signal PYE, which is generated internally in the semiconductor memory device, is activated at the end of a predetermined period of time (t1) which begins when a row active command is input. The period of time (t1) is the minimum amount of time required from the time the row address strobe signal /RAS becomes active until the bit line sensing operation is executed. The timing control signal PYE prevents a column line from being selected before the bit line sensing operation is executed. The inverter 120 inverts the timing control signal PYE, and the NOR gate 130 performs a logical sum operation with respect to the output of the inverter 110 and the output of the inverter 120 and then inverts the result. The NAND gate 140 receives an internal clock signal PCLKCD and the output of the NOR gate 130 as inputs. The inverter 150 inverts the output of NAND gate 140 to output a column select line enable signal PCSLEi. Therefore, the column select line enable circuit of the semiconductor memory device shown in FIG. 1 allows the internal clock PCLKCD to pass therethrough when the corresponding bank is selected and the timing control signal PYE is at a "high" level. The internal clock PCLKCD is generated internally in the chip in accordance with the system clock CLK which is applied from outside of the semiconductor memory device.
FIGS. 2 and 3 are timing diagrams showing waveform of various signals for a burst read operation in which several bits of data are read sequentially and continuously from the semiconductor memory device.
FIG. 2 is a timing diagram showing waveforms of various signals for a case in which the minimum tRCD required by the column select line enable circuit of FIG. 1 is satisfied. In FIG. 2, the internal clock PCLKCD is generated according to the system clock CLK which applied from outside of the memory device. The timing control signal PYE is activated a predetermined period of time t1 after a row active command is applied. The decoded bank address signal DBAi is activated a predetermined period of time after a read command is applied. The column select line enable signal PCSLEi undergoes level transitions in response to the internal clock PCLKCD when the timing control signal PYE and the decoded bank address signal DBAi are both at a "high" level.
FIG. 3 a timing diagram showing waveforms of various signals for a case in which the minimum tRCD required by the column select line enable circuit of FIG. 1 is not satisfied. In FIG. 3, tRCD calculated based on the predetermined period of time (t1) is 3 cycles, but the read command is applied only 2 cycles after the row active command is applied. The timing control signal PYE is triggered responsive to the row active command, and the decoded bank address signal DBAi is generated responsive to the bank address input with the read command. When the bank address is decoded, the column address is also decoded. Therefore, when the decoded bank address signal of the bank A is at a "high" level, the column select line corresponding to the pertinent column address must be activated.
However, as shown in FIG. 3, if the timing control signal PYE is inactive, even when the decoded bank address signal DBAi is activated, an active pulse corresponding to the data bit "n" is not generated in the column select line enable signal PCSLEi. Referring to FIG. 1, the timing control signal PYE is delayed by gates 120 and 130, and when t1 is too long, both inputs to gate 140 are not high at the same time, or are not both high long enough, to generate a high pulse at the output of inverter 150. In other words, when t1 is too long, PYE is not activated soon enough for clock pulse in PCLKCD to propagate through to PCSLEi. Thus, the first pulse of PCSLEi (which should have occurred at the time shown in broken lines in FIG. 3) is missed, and the first bit of data in a burst read operation is not output from the semiconductor memory device.
Accordingly, a need remains for a technique for overcoming the problems described above.